1. Field of Invention
The present invention relates to the manufacture of semiconductor devices, and in particular to methods of preventing dopant depletion in active regions of such devices built on semiconductor-on-insulator (SOI) substrates.
2. Description of the Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate electrode to control an underlying surface channel joining a source and a drain. The channel, drain and source are located in a semiconductor substrate, with the channel being doped oppositely to the drain and source. The gate electrode is separated from the semiconductor substrate by a thin insulating layer (i.e., a gate dielectric layer) such as an oxide. The operation of the IGFET involves application of an input voltage to the gate electrode, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET fabrication processes, the source and drain are formed by introducing dopants of a second conductivity type (P or N) into the semiconductor substrate of a first conductivity type (N or P) using a mask. Other steps of IGFET fabrication processes, such as annealing, involve elevated temperatures.
For IGFETs built on SOI substrates, dopant migration into the buried oxide tends to occur during high temperature processing. This dopant migration occurs at higher rates for dopant materials with low atomic weights, such as boron. As active surface semiconductor regions get increasingly thin, as in a fully-depleted SOI devices, the dopant migration can lead to undesirable front channel doping changes, as well as undesirable lowering of the threshold voltage of the unwanted back channel region.
A semiconductor-on-insulator (SOI) device includes a buried insulator layer and an overyling semiconductor layer. Portions of the insulator layer are doped with the same dopant material, for example boron, as is in corresponding portions of the overlying surface semiconductor layer. A peak concentration of the dopant material may be located in the insulator material, or may be located in a lower portion of the surface semiconductor layer. The dopant material in the insulator layer may prevent depletion of dopant material from portions of the surface semiconductor layer, such as from channel portions of NMOS transistors.
According to an aspect of the invention, a semiconductor-on-insulator (SOI) device includes a surface semiconductor layer and a buried insulator layer beneath the surface semiconductor layer. A portion the surface semiconductor layer and a portion of the insulator layer are both doped with a dopant material, and wherein the portion of the semiconductor layer and the portion of the insulator layer are in contact with each other.
According to another aspect of the invention, a semiconductor-on-insulator (SOI) device includes a surface semiconductor layer having a surface channel region which includes a dopant material; and means for reducing loss at elevated temperatures of the dopant material from the surface channel region.
According to yet another aspect of the invention, a method of preventing migration of a dopant material from a channel region of a surface semiconductor layer of a semiconductor-on-insulator (SOI) device, includes the steps of: implanting the dopant material in a buried doped portion of the SOI device; and forming the channel region above the doped portion.